Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

Multiple, independent clocks are ubiquitous in system-on-chip (SoC) design. Most SoC devices have multiple interfaces, some following standards that use very different clock frequencies. Many modern ...

Here are some of the main reasons why metastability may occur in our designs and some of the ways in which we can mitigate its effects In my previous column, we introduced the concept of setup and ...